Example embodiments of inventive concepts relate to semiconductor devices, and more particularly to delay locked loop circuits included in semiconductor devices and methods of operating the delay locked loop circuits.
Generally, a clock signal is widely used as a signal for synchronizing an operating timing of a semiconductor device. When a clock signal applied from an external device is used inside a semiconductor device, a time delay or a clock skew by internal circuits may occur. A delay locked loop (DLL) circuit may perform a function that synchronizes an internal clock signal with an external clock signal by compensating for this time delay. In particular, the DLL circuit is widely used in a synchronous memory device, such as a synchronous dynamic random access memory (SDRAM) that requires the synchronous operation for the clock signal. However, as an operating speed of a semiconductor device increases, a phenomenon where the clock signal is distorted such that a duty cycle (or a duty ratio) of the clock signal is not maintained as about 50% frequently occurs, which results in an abnormal operation of a double data rate (DDR) SDRAM using both rising and falling edges of the clock signal. Thus, the DLL circuit used in the DDR SDRAM should perform not only the locking for synchronizing the clock signal but also duty cycle correction (DCC). However, in a case where the DCC is performed along with the locking, the DCC may affect the locking, which may result in an operation error.